PCBs, laminate chip carriers, and the like permit formation of multiple circuits in a minimum volume or space. Such structures typically comprise a stack of layers of signal, ground and/or power planes (lines) separated from each other by a layer of dielectric material. The lines on one plane are often in electrical contact with those on another plane by plated holes passing through the dielectric layers. The plated holes are often referred to as “vias” if internally located, “blind vias” if extending a predetermined depth within the board from an external surface, or “plated-thru-holes” (PTHs) if extending substantially through the board's full thickness.
Conventional processes of making PCBs, chip carriers and the like typically comprise fabrication of separate inner-layer circuits (circuitized layers), which are formed by coating a photosensitive layer or film over a copper layer of a copper clad inner-layer base material. The photosensitive coating is imaged, developed and the exposed copper is etched to form the desired number of conductor lines or other features such as power and ground planes patterns. The photosensitive film is then stripped from the copper, leaving the circuit pattern on the surface of the inner-layer base material. Often, this methodology is referred to as photolithographic processing in the PCB art. Added description is not believed necessary in view of such known teachings.
With an established number of such structures formed, a multilayered stack of these may now be produced by preparing a lay-up of inner-layers, ground planes, power planes, etc., typically separated from each other by a layer of conventional dielectric “pre-preg” material, which usually includes a layer of glass cloth (fiberglass) impregnated with a partially cured material (e.g., a “B-stage” epoxy resin). The outermost (top and bottom) layers of the multilayered “stack” usually comprise copper clad, glass-filled, epoxy planar substrates with the copper cladding comprising the exterior surfaces of the stack. This stack is laminated to form a monolithic structure using heat and pressure to fully cure the B-stage resin. As understood, the resulting stack typically has metal (usually copper) cladding on both of its exterior surfaces. Exterior circuit layers are formed in the copper cladding using procedures similar to the procedures used to form the inner-layer circuits. In a well known such procedure, a photosensitive film is applied to the copper cladding, exposed to patterned activating radiation, and developed. An etchant such as cupric chloride may then be used to remove copper bared by the development of the photosensitive film. Finally, the remaining photosensitive film is removed to provide the exterior circuit layers. Various elements of these outer layers, such as pads, may then be electrically coupled to selected electronic components mounted on the structure, such components including capacitors, resistors, modules, and the like, including even semiconductor chips.
Electrically conductive thru-holes (or “interconnects”, as often referred to in the industry) are used to electrically connect individual circuit layers within the structure to each other and/or to the outer surfaces, these thru-holes passing through all or a portion of the “stack”. Thru-holes are generally formed prior to the formation of circuits on the exterior surfaces by drilling holes through the stack at appropriate locations. Following several pre-treatment steps, the walls of the holes are typically catalyzed by contact with a plating catalyst and metallized, typically by contact with an electro-less or electrolytic copper plating solution to form conductive pathways between circuit layers. Following formation of the conductive thru-holes, exterior circuits, or outer conductive layers are formed using the above procedure(s).
When the above multilayered substrate has been formed with its multiple conductive circuit layers and alternating dielectric layers, the aforementioned semiconductor chips and/or other electrical components (e.g., resistors, capacitors, and even including chip carriers in the case of multilayered PCBs) are mounted at appropriate locations on the exterior circuit layers of the multilayered structure, typically using solder mount pads to bond the components. These components are usually in electrical contact with the circuits within the structure through the thru-holes, as desired. Such solder pads are typically formed by coating an organic solder mask coating over the exterior circuit layers. The solder mask may be applied by screen coating a liquid solder mask coating material over the surface of the exterior circuit layers using a screen having openings defining areas where solder mount pads are to be formed. Alternatively, a photoimageable solder mask may be coated onto the board and then exposed and developed to yield an array of openings defining the pads. The openings are then coated with solder using processes known to the art, one known process being wave soldering.
As is known in the industry, the relative complexity of various product designs has increased significantly in recent years. Mainframe computer PCBs, for example, may require as many as thirty-six layers of circuitry or more, with the complete structure having a thickness of as much as about 0.250 inch (250 mils). Chip carriers, designed to carry one or more semiconductor chips thereon, also require more conductive layers and more complex circuit designs. These products have been typically designed with about three or five mil wide signal lines and twelve mil diameter thru-holes. For increased circuit densification in many of today's products, however, the industry desires to reduce signal lines to a width of only about two mils or less and thru-hole diameters to two mils or less. The substrate industry also desires to avoid manufacturing problems frequently associated with such more complex products, as is understandable. For example, many current processes utilize inner-layer materials that are glass-reinforced resin or other suitable dielectric material, clad with metal (typically copper) on both surfaces.
Glass-reinforcing material, typically utilizing continuous or semi-continuous strands of fiberglass which extend throughout the width and length of the overall final substrate, is used to contribute strength and rigidity to the final stack. If continuous, these fiberglass strands commonly run the full width (or length) of the structure and include no breaks or other segments as part thereof. Thus, by the term “continuous” as used herein to define fibrous materials is meant a structure such as a woven cloth of lengthy fibers, including fibers which, as stated, typically run the full distance through the structure. By the term “semi-continuous” is meant structures with much shortened length fibers, which are also referred to as “chopped” fibers, such as chopped fiber mats. Such fibrous materials occupy a relatively significant portion of the substrate's total volume, a disadvantage especially when attempting to produce highly dense numbers of thru-holes and very fine line circuitry to meet new, more stringent design requirements. More specifically, when holes are drilled (typically using laser or mechanical drills) to form these needed thru-holes, end segments of the fiberglass fibers may extend into the holes during lamination, and, if so, must be removed prior to metallization. This removal, in turn, creates the need for additional pretreatment steps such as the use of glass etchants to remove the glass fibrils extending into the holes, subsequent rinsing, etc. If the glass is not removed, a loss of continuity might occur in the thru hole internal wall metal deposit. In addition, both continuous and semi-continuous glass fibers add weight and thickness to the overall final structure, yet another disadvantage associated with such fibers. Additionally, since lamination is typically at a temperature above 150° C., the resinous portion of the laminate usually shrinks during cooling to the extent permitted by the rigid copper cladding, which is not the case for the continuous strands of fiberglass or other continuous reinforcing material used. The strands thus take on a larger portion of the substrate's volume following such shrinkage and add further to complexity of manufacture in a high density product. If the copper is etched to form a discontinuous pattern, laminate shrinkage may not be restrained even to the extent above by the copper cladding. Obviously, this problem is exacerbated as feature sizes (line widths and thicknesses, and thru-hole diameters) decrease. Consequently, even further shrinkage may occur. The shrinkage, possibly in part due to the presence of the relatively large volume percentage of continuous or semi-continuous fiberglass strands in the individual layers used to form a final product possessing many such layers, may have an adverse affect on dimensional stability and registration between said layers, adding even more problems for the PCB manufacturer.
Glass fiber presence, especially those of the woven type, also substantially impairs the ability to form high quality, very small thru-holes using a laser, one of the most preferred means to form such thru-holes. Glass cloth has drastically different absorption and heat of ablation properties than typical thermo-set or thermo-plastic matrix resins. In a typical woven glass cloth, for example, the density of glass a laser might encounter can vary from approximately 0% in a window area to approximately fifty percent by volume or even more, especially in an area over a cloth “knuckle”. This wide variation in encountered glass density leads to problems obtaining the proper laser power for each thru-hole and may result in wide variations in thru-hole quality, obviously unacceptable by today's very demanding manufacturing standards. Glass fiber presence also often contributes to an electrical failure mode known as CAF growth. CAF (cathodic/anodic filament) growth often results in time dependent electrical shorting failure which occurs when dendritic metal filaments grow along an interface (typically a glass fiber/epoxy resin interface), creating an electrical path between two features which should remain electrically isolated. Whether continuous (like woven cloth) or semi-continuous (like chopped fiber mattes), glass fiber lengths are substantial in comparison to the common distances between isolated internal features, and thus glass fibers can be a significant detractor for PCB insulation resistance reliability. While the use of glass mattes composed of random discontinuous chopped fibers (in comparison to the longer fibers found in continuous structures) can largely abate the problem of inadequate laser drilled thru-hole quality, such mattes still contain fibers with substantial length compared to internal board feature spacing and, in some cases, offer virtually no relief from the problem of this highly undesirable type of growth. Many of today's semiconductor packaging substrates are composed of a inner woven glass cloth construction ranging from about 400 to 800 microns thick and include “build-up” layers atop one or both sides thereof in order to form dense packages. The resulting thick “core” is typically drilled using mechanical drilling and the pitch (hole-to-hole spacing) dimensions are rather large.
To address the glass fiber issue, alternative dielectric materials have been proposed, including, for example, one known as “expanded PTFE”, PTFE being the designate for polytetrafluoroethylene. A common example of such material is the well known material Teflon, sold by E. I. DuPont de Nemours and Company. In U.S. Pat. No. 5,652,055, for example, there is described an adhesive sheet (or “bond ply”) material suitable to serve as adhesive layers in a variety of adhesive applications, such as in circuit board laminates, multi-chip modules, and in other electrical applications. The adhesive sheet is described as being constructed from an expanded PTFE material, such as that described in U.S. Pat. No. 3,953,566. Preferably, the material is filled with inorganic filler and is constructed as follows: a ceramic filler is incorporated into an aqueous dispersion of dispersion-produced PTFE. The filler in small particle form is ordinarily less than forty microns in size, and preferably less than fifteen microns. The filler is introduced prior to co-coagulation in an amount that will provide ten to sixty percent, and preferably forty to fifty percent by weight filler in the PTFE, in relation to the final resin-impregnated composite. The filled PTFE dispersion is then co-coagulated, usually by rapid stirring. The coagulated filled PTFE is then added. The filled material is then lubricated with a common paste extrusion lubricant, such as mineral spirits or glycols, and then paste extruded. The extrudate is usually calendared, and then rapidly stretched 1.2 to 5000 times, preferably two times to 100 times, per this patent, at a stretch rate of over 10% per second, at a temperature of between 35 degrees C. and 327 degrees C. The lubricant can be removed from the extrudate prior to stretching, if desired. The resulting expanded, porous filled PTFE is then imbibed with adhesive by dipping, calendaring, or using a doctor blade on a varnish solution of about two to seventy percent adhesive in solvent. The wet composite is then affixed to a tenter frame, and subsequently “B-staged” at or about 165 degrees C. for 1 to 3 minutes. The resulting sheet adhesive typically consists of: (a) 9 to 65 weight percent PTFE; (b) 9 to 60 weight percent inorganic filler, in the form of particulate; and (c) 5 to 60 weight percent adhesive imbibed within the porous web structure.
Additional alternative dielectric materials suitable for use in circuitized substrates are described in certain ones of the following listed documents.
With particular respect to many conventional chip carriers, which mount directly onto PCBs, if the coefficient of thermal expansion (CTE) of the semiconductor chip, the organic chip carrier, and the printed circuit board are substantially different from one another, industry standard semiconductor chip array interconnections to the organic chip carrier may be subject to high stress during thermal cycling operation, thus presenting another possible problem to the manufacturer of such substrates. If solder ball connections (e.g., a ball grid array (BGA)) are used, as is well known, the formed solder interconnections between the organic chip carrier and printed circuit board may also be subject to high stress during operation. Significant reliability concerns may then become manifest by failure of the connections or even failure of the integrity of the semiconductor chip (also known as chip “cracking”). These reliability concerns significantly inhibit design flexibility. For example, semiconductor chip sizes may be limited, or interconnect sizes, shapes and spacing may have to be customized beyond industry standards to reduce these stresses. These limitations may limit the electrical performance advantages of the organic electronic package or add significant cost to the carrier-chip(s) electronic package. Typically, a semiconductor chip has a CTE of two-three parts per million per degree Celsius (ppm/.degree. C.) while a standard printed circuit board has a much greater CTE of 17-20 ppm/.degree. C.
Yet another possible concern for the chip carrier manufacturer is one of reliability, involving the surface redistribution layer which interfaces between the organic substrate and the semiconductor chip. This layer may be susceptible to stresses resulting from thermal cycling of the organic substrate together with a chip which is also solder coupled with the organic substrate. Such stresses result from a CTE differential between the surface redistribution layer and the remainder of the organic substrate. The ability of the surface redistribution layer to withstand such stresses depends on mechanical properties of the surface redistribution layer. If the redistribution layer cannot accommodate the thermal stresses, then the surface redistribution layer is also susceptible to deterioration, such as cracking, which can cause failure of interconnections between the carrier and chip, as well as between the carrier and PCB.
In addition to the above many possible concerns, there are environmental and safety concerns to be addressed. Some environmental concerns have arisen of late with respect to the use of halogens (e.g., bromine) and various solder compositions which contain lead as a component thereof. Existing and/or proposed legislation in Europe and Japan, for example, now prohibit such materials. Safety concerns include the flammability of substitute products, meaning the ability of the final product to become inflamed or burn, e.g., due to the presence of excessive heat and/or when operating under extremely high electrical loads. The latter concerns have long been recognized in the industry, which has in turn resulted in many dielectric materials possessing a flame retardant (“FR”) rating, e.g., “FR4.”
The following listing of patents includes those which describe various dielectric compositions and substrates including same, in addition to methods of making such substrates. The listing is not intended to represent that an exhaustive search of the art has been conducted nor is providing the listing an admission that any are prior art to the presently claimed invention.
In U.S. Pat. No. 7,270,845, there is defined a dielectric composition which forms a dielectric layer usable in circuitized substrates such as PCBs, chip carriers and the like. As such a layer, it includes a cured resin material and a predetermined percentage by weight of particulate fillers, thus not including continuous fibers, semi-continuous fibers or the like as part thereof. U.S. Pat. No. 7,270,845 is assigned to the same Assignee as the present invention.
In U.S. Pat. No. 7,145,221, there is defined a circuitized substrate comprising a first layer comprised of a dielectric material including a low moisture absorptive polymer resin in combination with a nodular fluoropolymer web encased within the resin, the resulting dielectric layer formed from this combination not including continuous or semi-continuous fibers as part thereof. The substrate further includes at least one circuitized layer positioned on the dielectric first layer. An electrical assembly and a method of making the substrate are also provided, as is an information handling system (e.g., computer) incorporating the circuitized substrate of the invention as part thereof. U.S. Pat. No. 7,145,221 is assigned to the same Assignee as the present invention.
In U.S. Pat. No. 7,078,816, there is defined a circuitized substrate comprising a first layer comprised of a dielectric material including a resin material including a predetermined quantity of particles therein and not including continuous fibers, semi-continuous fibers or the like as part thereof, and at least one circuitized layer positioned on the dielectric first layer. An electrical assembly and a method of making the substrate is also provided, as is a circuitized structure including the circuitized substrate in combination with other circuitized substrates having lesser dense thru-hole patterns. An information handling system incorporating the circuitized substrate of the invention as part thereof is also provided. U.S. Pat. No. 7,078,816 is assigned to the same Assignee as the present invention.
In U.S. Pat. No. 6,358,608, there are described various fire retardant and heat resistant yarns, fabrics, felts and other fibrous blends which incorporate high amounts of oxidized polyacrylonitrile fibers. Such yarns, fabrics, felts and other fibrous blends have a superior Limiting Oxygen Index (LOI) and Thermal Protective Performance (TPP) compared to some other fire retardant fabrics. The yarns, fabrics, felts and other fibrous blends is this patent are also described as being more soft and supple, and therefore more comfortable to wear, compared to conventional fire retardant fabrics. The yarns, fabrics, felts and other fibrous blends incorporate up to 99.9% oxidized polyacrylonitrile fibers, together with at least one additional fiber, such as p-aramid, in order to provide increased tensile strength and abrasion.
In U.S. Pat. No. 6,323,436, PCBs are prepared by first impregnating a non-woven aramid chopped fiber mat or a thermoplastic liquid crystalline polymer (LCP) paper instead of the reinforcement typically used in the electronics industry, described in this patent as a woven glass fabric. This aramid reinforcement matte is comprised of a random (in-plane) oriented mat of p-aramid (poly(p-phenylene terephthalamide)) fibers comprised of Kevlar (Kevlar is a registered trademark of E. I. duPont deNemours and Company), and has a dielectric constant of four as compared to 6.1 for standard E-glass cloth. The lower permittivity of the non-woven aramid reinforcement provides for faster signal propagation, allowing increased wiring density and less crosstalk, which becomes increasingly important for high I/O chips and miniaturization. Since the p-aramid fibers are transversely isotropic and have an axial CTE of about −3 to about −6 ppm/degree Celsius (hereinafter C.) when combined with a thermosetting resin, the final composite described in this patent is said to possess a CTE which can be controlled and adjusted to match that of silicon or semiconductor chips in the range of about 3 to about 10 ppm/degree C. The thermoplastic liquid crystal polymer (LCP) paper is a material called Vecrus (Vecrus is a registered trademark of Hoechst Celanese Corp.), which uses the company's Vectra polymer as part thereof (Vectra also being a registered trademark of Hoechst Celanese Corp.). According to this patent, the paper has a dielectric constant of 3.25, a dissipation factor of 0.024 at sixty Hertz (Hz), a UL 94-V0 rating and an in-plane CTE of less than 10 ppm/degree. C. The alleged advantages of this material over the aramid mat are the lower dielectric constant and very low moisture absorption, allegedly less than 0.02%. The non-woven aramid or LCP paper is used in conjunction with a thermosetting resin to form the final composite substrate. Examples of thermosetting resins useful in this patent include epoxy, cyanate ester, bismaleimide, bismaleimide-triazine, maleimide or combinations thereof. The resin-impregnated low CTE reinforcement is then partially cured to a “B”-stage to form the pre-preg, and then the pre-preg is cut, stacked, and laminated to form a sub-composite with exterior copper sheets.
In U.S. Pat. No. 6,207,595, there is described an example of a dielectric material composition for use in a PCB in which the dielectric layer's fabric material is made from a cloth member having a low enough content of particulates and a sufficient quantity of resin material to completely encase the cloth member including the particulates, so that the resin material extends beyond the highest protrusions of the cloth member (i.e. the fabric material is thicker and will pass a certain test standard (in '595, the known HAST level A test). Thus, the woven cloth is known to include a quantity of particulates, which term is meant in '595 to include dried film, excess coupler, broken filaments, and gross surface debris. The resin may be an epoxy resin such as one often used for “FR4” composites (“FR4” has become a conventional, abbreviated name for the resulting substrates and often also for the resins forming part thereof, and is based in part on the flame retardant (hence the “FR” designation) rating of these established products).
In U.S. Pat. No. 5,418,689, there is described a PCB product wherein the dielectric substrate can include a thermoplastic and/or thermosetting resin. Thermosetting polymeric materials mentioned in this patent include epoxy, phenolic base materials, polyimides and polyamides. Examples of some phenolic type materials include copolymers of phenol, resorcinol, and cresol. Examples of some suitable thermoplastic polymeric materials include polyolefins such as polypropylene, polysulfones, polycarbonates, nitrile rubbers, ABS polymers, and fluorocarbon polymers such as polytetrafluoroethylene, polymers of chlorotrifluoroethylene, fluorinated ethylenepropylene polymers, polyvinylidene fluoride and polyhexafluoropropylene. The dielectric materials may be molded articles of the polymers containing fillers and/or reinforcing agents such as glass filled polymers.
In U.S. Pat. No. 5,314,742, there is described the use of non-woven aramid sheets to provide reinforcement for the resulting laminate. The reinforcing aramid sheet is described as having a coefficient of thermal expansion (CTE) of less than 10 ppm per .degree. C. and is prepared from 75 to 95 wt. % p-aramid floc and from 5 to 25 wt. % poly(m-phenylene isophthalamide) fibrids. Floc is defined in U.S. Pat. No. 4,729,921. Para-aramid fibers are very high in strength and modulus. Examples of para-aramid fibers are set out in U.S. Pat. No. 3,869,429. Specific examples of para-aramid materials are poly(p-phenylene terephthalamide) (PPD-T) and copoly(p-phenylene-3,4′-oxydiphenylene terephthalamide). Fibers of PPD-T are generally made by an air gap spinning process such as described in U.S. Pat. No. 3,767,756, and are preferably heat treated as described in U.S. Pat. No. 3,869,430. Preferably, poly(p-phenylene terephthalamide) floc which has not been refined is utilized. High shear forces exerted on the fibers during processing, e.g., refining, may cause damage to the fibers and adversely affect the CTE of the reinforcement. It is also preferred to employ p-aramid floc of high orientation and relatively lower crystallinity. Fibrids are described in U.S. Pat. No. 4,729,921. To prepare the sheet, the floc and fibrids are dispersed in the desired proportions as an aqueous slurry, the solids concentration generally ranging between 0.005% and 0.02%. The slurry is not refined. The slurry can be made into paper by conventional means. In the examples mentioned in this patent, wet sheets were formed in an inclined wire Deltaformer papermaking machine and dried using heated drier cans. The dried sheets preferably had a basis weight between 0.8 and 4.0 oz/yd2, and were then calendered between two hard-surface rolls. Calender pressures between about 500 and 2500 kg/cm (nip pressure) and roll temperatures between about 130 and 150 degrees C. were used. The paper was then pre-pregged with a resin having a high glass transition temperature (Tg), e.g., above about 160 degrees C.
In U.S. Pat. No. 5,246,817, there is described one form of improvement in the manufacture of products such as PCBs. The manufacturing process in 5,246,817 consists of the sequential formation of layers using photosensitive dielectric coatings and selective metal deposition procedures. Imaged openings may be formed by exposure of a photosensitive dielectric coating to activating radiation through a mask in an imaged pattern, followed by a described development procedure. Alternatively, imaging may be by laser ablation, in which case, the dielectric material need not be photosensitive.
In U.S. Pat. No. 5,229,199, there is described a rigid composite comprising a polyester, phenolic, or polyamide resin matrix reinforced with woven fabric of continuous p-aramid filaments coated with from about 0.2 to five percent, by weight, of a solid adhesion modifier which reduces the adhesion between said resin matrix and said p-aramid filaments embedded therein, the adhesion modifier selected from the group consisting of a 2-perfluoroalkylethyl ester, a paraffin wax and a combination thereof. The coated filaments, when embedded in the matrix and tested in accordance with MIL-STD-662D, exhibit a ballistics limit from about 1000 to 4000 feet per second and a composite areal density from about 0.4 to six pounds per square foot.
The present invention as defined herein represents an improvement over products and processes such as those described above by the utilization of, among other things, a dielectric layer comprised of a p-aramid base paper impregnated with a low moisture absorption, halogen free resin for use in combination with a circuitized layer to form a circuitized substrate product. Significantly, the product will not include continuous or semi-continuous fiberglass fibers as part thereof. It is believed that such a product and method to make the product, as further defined herein, will represent significant advancements in the art.